The future of chip manufacturing involves creating denser and more complicated chip designs. The trend to maximize the performance of a chip has been to construct chips that incorporate more processing cores per chip. The manufacturing process for multi core chips is complex, and at least initially there is expected to be a fairly mediocre yield ratio of good or otherwise viable cores. The designers of future product families envision many cores per chip, each with their own cache hierarchy.
FIG. 1 illustrates a multi-core chip 100, having 4 processing cores 102, 104, 105 and 108, contained therein. Each processing core has 2 cache memory levels, L2 and L3 associated therewith. Thus Core 1 (102) has two levels of cache memory, L2 (112) and L3 (122) associated therewith as does Core 2 (104) has cache memory 114, and 124 associated therewith. Core 3 and Core 4 also each have a cache hierarchy associated therewith. Core 3 (105) has been determined to be a defective core and is garded out.
Typically, access to main memory involves populating the local cache with the data. The “local” cache is the cache associated with the processor with invoked the object's retrieval. Hardware hashing dictates where in the cache the data object will reside based on the local in mail memory of this object. Those hashing mechanisms don't involve which cache the data will be brought into because it is always assumed that the data will be placed in the local cache. Similarly, data that is migrated out of L2 cache, into L3, is not labeled with which L3 cache is should be stored in, because it is assumed that the data will always go into the local L3. These standards don't change regardless of whether or not the various caches are shared.
If anything on the processing core is found to be “bad” or otherwise defective during the firmware initialization the core will be “garded out” rendering the entire cache hierarchy for that defective core unusable. The “bad” hardware status can be something as simple as a single failed transistor or some other functional defect that will make the processing core fundamentally broken or unusable. During functional verification of a single chip it may be that out of 8 cores, 2 or 3 will be defective. Preferably those chips will not be discarded, but rather, placed in a machine in which the customer ordered a 4 way or 6 way machine.
The defective cores are simply not needed so the fact that they are garded out is of no concern. With continued reference to FIG. 1, Core 3 (105) is defective and is therefore garded out and is of no concern. The caching capabilities of the L2 (115) and L3 (125) are typically independent of the defective core and are not affected by the fact that the particular core they are attached to is defective. However, the caching capacity of the L2 (115) and L3 (125) local to a particular core is typically lost when that core is garded out as defective.